1. Field of the Invention
The invention relates to an apparatus and a method of detecting a synchronization signal while serial data having a fixed frame length is being transferred in a data processing apparatus such as a computer.
2. Description of the Related Art
An apparatus or a method of detecting a synchronization signal has been conventionally employed to ensure frame synchronization for correctly convert received serial data into parallel data while serial data having a fixed frame length is being transferred in a data processing apparatus such as a computer.
FIG. 1 is a block diagram of one of conventional apparatuses of detecting a synchronization signal. A clock extracting circuit 2 extracts clock elements from received serial data SD, and emits bit clocks BC in synchronization with the serial data SD. A shift register 1 receives the bit clocks BC from the clock extracting circuit 2, and shifts the content thereof or the serial data SD bit by bit by virtue of the bit clocks BC. Thus, the serial data is converted into parallel data PD.
A synchronization pattern detecting circuit 4 checks whether a synchronization pattern is found in the parallel data PD emitted from the shift register 1. If found, the synchronization pattern detecting circuit 4 emits a synchronization-detecting signal SS1. A synchronization circuit 3 is provided with a counter (not illustrated) therein, by which the bit clocks BC emitted from the clock extracting circuit 2 is counted, and emits word clocks WC for outputting parallelized data. The counter mounted in the synchronization circuit 3 is reset on receiving the synchronization-detecting signal, and compensates for a phase of the word clocks WC so that the parallel data PD is output on the basis of the synchronization pattern.
A latch 5 latched the content of the shift register 1 when the word clocks WC are received, and emits the parallel data PD.
Hereinbelow is explained an operation of the above-mentioned conventional synchronization signal detecting apparatus. The received serial data SD is input into the shift register 1 bit by bit in synchronization with the bit clocks BC emitted from the clock extracting circuit 2. The synchronization pattern detecting circuit 4 emits the synchronization-detecting signal SS1 when the content of the shift register 1 is in accord with the synchronization pattern.
The synchronization circuit 3 counts the bit clocks BC, and emits the word clocks WC in accordance with the count. When the synchronization circuit 3 receives the synchronization-detecting signal SS1 from the synchronization pattern detecting circuit 4, the counter (not illustrated) which counts the bit clocks BC is reset to thereby compensate for a phase of the word clocks WC. Thereafter, the latch 5 emits the content of the shift register 1 as the parallel data PD.
In the above-mentioned conventional apparatus of detecting a synchronization signal, if a wrong synchronization pattern caused by bit error and so on appears in a serial data while the serial data having a fixed frame length is being transferred, the apparatus could not distinguish a wrong synchronization pattern from a correct one. This results in a problem that the apparatus recognizes the wrong synchronization pattern as a correct one, and hence, correct parallel data is not emitted.
The reason of this is that the above-mentioned conventional apparatus of detecting a synchronization signal does have neither means for judging whether a synchronization pattern found in serial data is correct or wrong nor means for judging whether frame synchronization is established or not.
U.S. Pat. No. 5,228,065 has suggested an arrangement for producing a synchronizing pulse wherein a synchronizing pulse is produced on detection of a frame codeword or frame-structured binary signal consisting of a first word repeated a plurality of times and at least one second word. A demultiplexer divides the incoming signal into N words which are advanced in parallel through N shift registers of a first memory matrix, followed by the next N words, and so on. A decoder determines whether the first word is stored in each register, and increments a respective one of N counters when the word is found. An addressing logic transforms the output into a binary number which controls a multiplexer which, in turn controls arrangement of bits in a second memory matrix. A synchronizing pulse is produced when the second memory matrix contains predetermined bits of the first and second word.
Japanese Unexamined Patent Publication No. 60-219835 has suggested a frame synchronizing circuit. The circuit is employed for a multiplexer for multiplying a plurality of low-speed data signals into a single high-speed data signal and dividing a single high-speed data signal into a plurality of low-speed data signals, and used when a single high-speed data signal is divided into a plurality of low-speed data signals. The circuit includes a first circuit for emitting a signal representing a position of a frame synchronization signal in the high-speed data signals, a second circuit for extracting a frame synchronization signal out of the high-speed data signals by virtue of a signal emitted from the first circuit, a third circuit for judging whether a signal extracted in the second circuit is a correct frame synchronization signal, and a fourth circuit for counting the number of outputs from the third circuit, and judging that frame synchronization is established when the count is over a first threshold value and that frame synchronization is broken when the count is over a second threshold value. The first circuit is made to stop in a predetermined condition, while the frame synchronization is not established, until the frame synchronization signal is detected out of the high-speed data signals, and is forced to start when the frame synchronization signal is detected. The first circuit is also made to stop in a predetermined condition when a signal having been extracted out of the high-speed data signals is not a correct frame synchronization signal. The third and fourth circuits are constituted in a single microprocessor.
Japanese Unexamined Patent Publication No. 61-257038 has suggested a frame synchronization circuit including a serial/parallel converting circuit for converting a single high-speed data having a bit rate of f.sub.0 into n parallel data each having a bit rate of f.sub.0 /in, a phase-shifting circuit for the parallel data into n-phase parallel data, n frame synchronization signal extracting circuits for extracting a frame synchronization signal for each of the n-phase parallel data, a frame position pulse generating circuit for generating a frame position pulse representing a position of the frame synchronization signal by virtue of bit clocks having a bit rate of f.sub.0 /n, n judgement circuits for judging whether a signal having been extracted by the frame synchronization signal extracting circuit is a correct frame pulse by virtue of the frame position pulse, n counter circuits for counting outputs from the judgement circuits, and judging that frame synchronization is established when positive outputs are over a first threshold value and that frame synchronization is broken when negative outputs are over a second threshold value, and a control circuit for stopping the frame position pulse generating circuit when frame synchronization is broken, and starting the frame position pulse generating circuit when the extracted signal is detected.
Japanese Patent Publication No. 62-28621 has suggested a synchronization circuit including first means for converting a time series data pulse signal containing a synchronization pattern having a plurality of bits into a plurality of parallel phase signal series, and second means for judging whether the parallel phase signal series are synchronization patterns. The synchronization circuit monitors from which phase signal series is detected a synchronization pattern at every synchronization pattern period, to thereby establish frame synchronization.
Similarly, Japanese Unexamined Patent Publications Nos. 62-213336, 63-30039, 63-262939, 3-46840, 5-276151, and 5-276153 have suggested an apparatus or a circuit for detecting a synchronization signal to thereby establish frame synchronization.